The present invention relates generally to magnetic memory devices and, more particularly, to a maskless array protection (AP) process flow that enables formation of interconnect vias and self-aligned contact to magnetic random access memory (MRAM) devices.
Magnetic (or magneto-resistive) random access memory (MRAM) is a non-volatile random access memory technology that could potentially replace the dynamic random access memory (DRAM) as the standard memory for computing devices. The use of MRAM as a non-volatile RAM will eventually allow for xe2x80x9cinstant onxe2x80x9d systems that come to life as soon as the system is turned on, thus saving the amount of time needed for a conventional PC, for example, to transfer boot data from a hard disk drive to volatile DRAM during system power up.
A magnetic memory element (also referred to as a tunneling magneto-resistive, or TMR device) includes a structure having ferromagnetic layers separated by a non-magnetic layer (barrier), and arranged into a magnetic tunnel junction (MTJ). Digital information is stored and represented in the memory element as directions of magnetization vectors in the magnetic layers. More specifically, the magnetic moment of one magnetic layer (also referred to as a reference layer) is fixed or pinned, while the magnetic moment of the other magnetic layer (also referred to as a xe2x80x9cfreexe2x80x9d layer) may be switched between the same direction and the opposite direction with respect the fixed magnetization direction of the reference layer. The orientation of the magnetic moment of the free layer are also known xe2x80x9cparallelxe2x80x9d and xe2x80x9cantiparallelxe2x80x9d states, wherein a parallel state refers to the same magnetic alignment of the free and reference layers, while an antiparallel state refers to opposing magnetic alignments therebetween.
Depending upon the magnetic state of the free layer (parallel or antiparallel), the magnetic memory element exhibits two different resistance values in response to a voltage applied across the tunnel junction barrier. The particular resistance of the TMR device thus reflects the magnetization state of the free layer, wherein resistance is xe2x80x9clowxe2x80x9d when the magnetization is parallel, and xe2x80x9chighxe2x80x9d when the magnetization is antiparallel. Accordingly, a detection of changes in resistance allows a MRAM device to provide information stored in the magnetic memory element (i.e., a read operation). In addition, a MRAM cell is written to through the application a bi-directional current in a particular direction, in order to magnetically align the free layer in a parallel or antiparallel state.
A practical MRAM device integrates a plurality of magnetic memory elements with other circuits such as, for example, control circuits for the magnetic memory elements, comparators for detecting the states in the magnetic memory elements, input/output circuits and miscellaneous support circuitry. As such, there are certain microfabrication processing difficulties to be overcome before high capacity/density MRAM products become commercially available. For example, in order to reduce the power consumption of the device and provide the variety of support functions CMOS technology is required. As is known in the art, various CMOS processing steps (such as annealing implants) are carried out at relatively high temperatures (e.g., in excess of 300Âxc2x0 C.). On the other hand, ferromagnetic materials employed in the fabrication of MRAM devices, such as CoFe and NiFeCo for example, require substantially lower process temperatures in order to prevent intermixing of magnetic materials. Thus, the magnetic memory elements are designed to be integrated into the back end wiring structure following front end CMOS processing.
Magnetic memory elements contain components that are easily oxidized and also sensitive to corrosion. To protect magnetic memory elements from degradation and ensure the performance and reliability of the MRAM device, it is desirable to form a passivation layer thereupon. In addition, a magnetic memory element includes very thin layers, some on the order tens of angstroms thick. Because the performance of the magnetic memory element is particularly sensitive to the surface conditions on which magnetic layers are deposited, it is desirable to maintain an atomically flat surface to prevent degradation of the MRAM device characteristics.
Notwithstanding the above described processing variations between ferromagnetic materials and conventional DRAM elements, it is nonetheless desirable to simplify the MRAM fabrication process and increase the compatibility thereof with conventional back-end-of-line (BEOL) metallization process sequences. The BEOL metallization process sequence commonly utilizes copper as the metallic conductor, but is not limited to this conductor material. Wiring features are formed by filling etched recesses in the interlevel dielectric (ILD) with metal and removing the extraneous metal by polishing the wafer to a flat surface leaving the filled features separated by ILD. The mesa structure of the fabricated MTJ device results in a step height differential between the MTJ device array and surrounding support area. For a variety of reasons, it is important to maintain the planarity of each level of back end wiring, and the array step height necessitates an additional planarization step before the next metallization level is formed. It is highly desirable to reduce the cost and seamlessly integrate the MRAM array and support structure into a back end wiring process. Moreover, this also requires the MRAM process to be compatible with low dielectric constant (low-k) interlevel dielectric materials.
In general, the material chosen to encapsulate the MTJ device may not be the ILD material used to support the BEOL wiring structure. Prior art teaches a fabrication method that separates the array region comprising the MTJ storage devices and the surrounding support area. While the prior art is a workable method, there are cost and performance issues associated therewith, as addressed hereinafter.
The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by a method for forming interconnect structures in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. An encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.
In another aspect, a method for forming back end of line (BEOL) interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A first dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Thereafter, the first dielectric layer is planarized down to the top of the MTJ stacks. A via opening is then defined in the first dielectric layer, thereby exposing a portion of said lower metallization layer. A second dielectric layer is formed over the first dielectric layer and over the exposed portion of said lower metallization layer. Then, a planar interlevel dielectric (ILD) layer is deposited over the second dielectric layer, and openings are formed within the ILD layer, over the array of MTJ stacks and the via opening.
In still another aspect, a method for forming back end of line (BEOL) interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A passivation layer is formed over the array of MTJ stacks and the lower metallization level. An encapsulating dielectric layer is then formed over the passivation layer, the encapsulating dielectric layer and the passivation layer being planarized to the top of the MTJ stacks. A dielectric mask layer is formed over the passivation layer, the encapsulating dielectric layer and the MTJ stacks, and a via opening is defined in the dielectric mask layer, thereby exposing a portion of the encapsulating dielectric layer. Then, a planar interlevel dielectric (ILD) layer is deposited over the dielectric mask layer, and openings are formed within the ILD layer and over the array of MTJ stacks and the via mask openings.